PCI Express
Introduction
PCI Express (Peripheral Component Interconnect Express), commonly abbreviated as PCIe, is a high-speed serial computer expansion bus standard. It is designed to replace the older PCI, PCI-X, and AGP bus standards. PCIe has numerous advantages over these older bus standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism, and native hot-plug functionality read more about hot-plug functionality.
History
PCI Express was developed by the PCI-SIG (PCI Special Interest Group), an association of over 900 companies that also developed the original PCI, PCI-X, and AGP standards. The PCIe 1.0 was officially released on 29th April 2002, and the latest version, PCIe 5.0, was released in 2019. The development of PCIe was primarily driven by the need for a faster and more efficient interface, as the older PCI and AGP standards were not able to keep up with increasing demands for bandwidth.
Architecture
PCI Express is a layered protocol, consisting of a transaction layer, a data link layer, and a physical layer. The transaction layer is responsible for the assembly and disassembly of the packets. The data link layer is responsible for data integrity over the physical layer, and the physical layer is responsible for managing the electrical and logical connections to the physical medium.
Transaction Layer
The transaction layer of PCIe is responsible for packet assembly before sending them out, and disassembly when the packets are received. It is also responsible for managing the traffic on the bus, ensuring that the data is sent and received in the correct order, and managing the quality of service.
Data Link Layer
The data link layer is responsible for the integrity of data sent over the physical layer. It achieves this through a sequence of transaction layer packets (TLPs), which are encapsulated within data link layer packets (DLLPs). The data link layer also provides an acknowledgment mechanism to ensure reliable data transfer.
Physical Layer
The physical layer of PCIe is responsible for the electrical and logical connection to the bus. It is divided into two sub-layers: the physical media attachment (PMA) layer, which includes functions such as signal detection and synchronization, and the physical coding sublayer (PCS), which includes functions such as 8b/10b encoding and scrambling.
Form Factors
PCI Express devices can come in several different form factors, including the full-height and half-height sizes for desktop computers, and the Mini Card and M.2 sizes for laptops. The form factor of a PCIe device determines its physical size and shape, as well as the number of lanes it can use.
Lanes
In PCIe, a 'lane' is a serial data connection that consists of two differential signaling pairs: one pair for receiving data, and the other for transmitting. Each lane is capable of simultaneous transmission and reception of data. The number of lanes (x1, x4, x8, x16, x32) directly influences the speed and bandwidth of the connection.
Speed and Bandwidth
The speed and bandwidth of a PCIe connection depend on the number of lanes and the version of the PCIe standard used. For example, a PCIe 3.0 connection with 16 lanes (x16) can achieve a maximum theoretical bandwidth of 15.75 GB/s, while a PCIe 4.0 connection with the same number of lanes can achieve a maximum theoretical bandwidth of 31.5 GB/s.
Applications
PCI Express is used in a wide range of applications, from high-performance graphics cards and network interface cards to SSDs and Wi-Fi/Bluetooth cards. It is also used in servers for high-speed network and storage connectivity, and in data centers for high-performance computing.
Future Development
The PCI-SIG has already announced the development of the PCIe 6.0 standard, which is expected to double the bandwidth of PCIe 5.0. This will continue the trend of each new version of PCIe doubling the bandwidth of the previous version, ensuring that PCIe can continue to meet the increasing demands for high-speed data transfer.